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C4I Publication Abstracts
Communications

C3I-3001

On the Relationship Between Measures of Discrimination
and the Performance of Suboptimal Detectors

Authors: Geoffrey C. Orsak and Bernd-Peter Paris

The problem of designing and analyzing suboptimal detectors via statistical distance measures is considered in this paper. As a preliminary result, we show that only the minimum and maximum probability of error are valid measures of discrimination between the input statistics. This result would seem then to imply that the use of distance measures in this context can be inappropriate. However, to overcome this apparent obstacle, we demonstrate explicit relationships between various f- divergences and the loss in performance of an arbitrary detector relative to the optimal detector. In particular, we establish both upper and lower bounds on the performance loss of a suboptimal detector in terms of the "distance" between the pertinent statistics of both the optimal and suboptimal detectors. While designing detectors by minimizing these upper bounds can be an elusive task, in many practical cases, the lower bound presented herein holds with equality. In this case, maximizing the separation of the output statistics of the detector with respect to a particular f-divergence equivalently minimizes the resulting probability of error of the detector. To facilitate design, other researchers have established conditions under which one may design arbitrary detection strategies with respect to a specified f-divergence (Kullback-Leibler distance is a principal example). We extend this approach by deriving necessary and sufficient conditions under which one may design detection strategies with respect to an arbitrarily chosen divergence. Thus when these conditions are met, one may optimize a detector with respect to the most analytically tractable distance measure to obtain the minimum probability of error detector over a selected class of detection strategies. Examples demonstrating the utility of this theory for the problem of designing optimal linear detectors and optimal signal sets are presented.

IEEE Transactions on Information Theory, Vol. 41, No. 1, pp. 188-203, January 1995.

C3I-3001

Channel Sharing Strategy
for Cellular Communications Networks

Authors: W. G. Evans, Jr. and Bernd-Peter Paris

Cellular Communications Networks are increasingly popular in today's society. However, the added mobility provided by these networks has a price. The spectrum used by these systems is strictly limited, which forces designers to seek new methods to utilize the limited resources in the most efficient manner. This study examines a channel allocation strategy that provides optimum network performance at a cost of a moderate increase in co-channel interference.

C3I-3002

Finite Precision Decorrelating Receivers
for Multi-User CDMA Communications Systems

Author: Bernd-Peter Paris

The design of single-user decorrelating receivers employing finite-precision sequences for despreading is considered. The problem is formulated as a non-linear bounded integer optimization problem which is shown to be NP-hard. A branch-and-bound algorithm for finding the best finite-precision decorrelating sequence is described. Numerical examples demonstrate that the loss in performance between the optimum, infinite-precision and the best finite-precision decorrelator is small even for large channel occupancies. Some sub-optimum algorithms are investigated which greatly reduce the computational complexity associated with finding good finite-precision decorrelator sequences.

Supported in part by the National Science Foundation under Grant NCR-9309044 and by Rome Laboratories under contract F30602-92-C-0053.

This work was presented in part at the 1994 IEEE International Symposium of Information Theory in Trondheim, Norway.

C3I-3004

Smart Pixel Based Viterbi Decoder

Authors: Michael W. Haney, ECE Department, George Mason University; Marc P. Christensen, BDM Federal, Inc.

As voice and data communications networks proliferate, they face ever increasing demands for reliability, portability, and bandwidth. In many applications, the transmitted power is limited by practical considerations. Examples include satellite, cellular, and undersea long haul fiber communications systems. In these applications Forward Error Correction (FEC) techniques may be used to achieve reliable communications within the constrained power. FEC techniques are ultimately limited in their performance by the conflicting requirements of high speed, high computational complexity, and low size and power consumption. VLSI implementations of the elegant and powerful Viterbi convolutional decoding algorithm (VA), which uses a recursive parallel search computation, are limited by the massive intra- and inter-chip communications requirements between nodes of the search graph. This constraint limits the number of states (nodes of the VA graph) for high-speed applications, and hence the overall performance of the VA. Current high speed single chip VLSI implementations are limited to a convolutional constraint length of about 7 and therefore require 27=128 processing nodes. Incrementing the constraint length by 1 provides nearly an order of magnitude improvement in BER, but requires twice as many computational and communications resources -- beyond the capabilities of a single chip. This size constraint limits single chip VLSI implementations to a coding gain of ~7 dB. Strong motivation exists for using longer constraint length codes, requiring several decoding ICs. A multi-chip VLSI VA implementation is impractical for high speed applications due to the inter-chip communications bottleneck. The approach discussed in this paper overcomes this limitation by employing free-space optical interconnects to provide the required inter-chip connection, while maintaining on-chip speeds between chips. A free-space optically interconnected Viterbi decoding architecture is described. Smart pixel design issues and a proof-of-concept demonstration are reviewed.

Digest of the Optical Society of America's Topical Meeting on Optical Computing, March, 1995.

C3I-3005

Free Space Optical Sliding Banyan Network

Authors: Michael W. Haney, ECE Department, George Mason University; Marc P. Christensen and James J. Levy, BDM Federal, Inc.

There is an ever increasing demand for high throughput, cost effective, broadband data switching networks, as demonstrated by the explosive growth in the Asynchronous Transfer Mode (ATM) equipment industry. Future networks must handle thousands of high bandwidth channels, implying an aggregate capacity in the terabit/second regime. These requirements will exceed the ability of VLSI based switching technology. Self-routing Banyan based networks, which utilize a deflection algorithm to efficiently route packets to their destinations while minimizing resources for a given blocking rate, have been proposed. To minimize latency and switching resources, the deflection routing approach requires an available output driver at each node at each stage. Smart pixel based free-space optical interconnections have been shown to provide the necessary interstage connections for this architecture, thereby eliminating the need for thousands of bulky, power hungry electrical interconnections. In this paper the Sliding Banyan (SB), a 3-D optical Multi-stage Interconnection Network (MIN) architecture, is evaluated and experimental aspects of the network are presented. The SB is a pipelined MIN based on identical perfect shuffle interconnections between stages. Since it is a Banyan, simple destination tag routing can be employed by setting the switches at each stage according to the destination address located in the header. If a conflict occurs between two packets, a prioritization scheme resets the destination address decoder to the first bit for the lower priority packet. The SB utilizes a unique 3-D partitioning of resources, which provides for efficient packet routing in a deflection routing scheme, while minimizing the number of line drivers. Rather than the traditional physically separated stages, in which the switching and I/O resources are distributed longitudinally, the SB's resources are distributed laterally, in the same physical plane. In this configuration the multiple stages of the switching fabric are physically interleaved, such that all stages for a given node reside in close proximity (i.e., on the same chip). This partitioning utilizes a single macro-optical shuffle interconnection module, which is simultaneously used by all stages. Simulations of unity permutation traffic were shown to achieve 10-12 blocking probability in 30 stages for a 1024 node network. This is a 50% reduction in the number of stages over a Tandem Banyan.

Digest of the Optical Society of America's Topical Meeting on Photonics in Switching, March, 1995.